Purpose
The RT5047A is a highly integrated voltage regulator and interface IC, specifically design for supplying power and control signals from advanced satellite set-top box (STB) modules to the LNB down-converter in the antenna dish or to the multi-switch box. This document explains the function and use of the RT5047A evaluation board (EVB), and provides information to enable operation, modification of the evaluation board and circuit to suit individual requirements.
Introduction
General Product Information
The device is consists of the independent current-mode boost controller and low dropout linear regulator along with the circuitry required for 22kHz tone shaping to support DiSEqC™ 1.x communications. The RT5047A provides fault protections including over-current, over-temperature and under-voltage lockout.
The RT5047A is available in a SOP-8 (Exposed Pad) package to achieve optimized solution for thermal dissipation.
Product Feature
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Wide Input Supply Voltage Range : 8V to 16V
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Output Current Limit of 550mA with 45ms timer
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Low Noise LNB Output Voltage (13.3V and 18.3V by SEL Pin)
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±3% High Accuracy for 0mA to 500mA Current Output
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Push-Pull Output Stage minimizes 13.3V to 18.3V and 18.3V to 13.3V Output Transition Time
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External 22kHz Tone Input
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Meet DiSEqC™ 1.x Protocol
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Output Short Circuit Protection
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Over-temperature Protection
Key Performance Summary Table
Key Features
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Evaluation Board Number : PCB014_V1
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Default Input Voltage
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12V
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Max Output Current
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500mA
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Default Output Voltage
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Low is for 13.3V, high is for 18.3V
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Default Marking & Package Type
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RT5047AGSP, SOP-8 (Exposed Pad)
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Operation Frequency
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700kHz (Typ.)
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Bench Test Setup Conditions
Headers Description and Placement
Please carefully inspect the EVB IC and external components, comparing them to the following Bill of Materials, to ensure that all components are installed and undamaged. If any components are missing or damaged during transportation, please contact the distributor or send e-mail to evb_service@richtek.com
Test Points
The EVB is provided with the test points and pin names listed in the table below.
Test point/
Pin name
|
Signal
|
Comment (expected waveforms or voltage levels on test points)
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LNB
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LNB output pin
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Output Voltage for LNB. Output capacitor should not higher than 4.7µF.
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BOOST
|
Boost feedback point
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Boost Output and Tracking Supply Voltage to LNB.
|
LX
|
Switch node
|
Switching Node of DC/DC Boost Converter.
|
VIN
|
Input voltage
|
Power Supply Input.
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EN
|
Enable point
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High to enable the LNB and low to disable the LNB.
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SEL
|
Output level select point
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Low for VLNB is 13.3V and high for VLNB is 18.3V.
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FAULT
|
Fault detect point
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Open drain. Pull to 3.3V by 4.7kΩ resistor. This pin will pull to low when OCP trigger.
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TONE
|
TONE input signal
|
Supply a 22kHz signal at this pin to control the output tone signal.
|
GND
|
Ground
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The Exposed Pad must be soldered to a large PCB and connected to GND for maximum power dissipation.
|
Power-up & Measurement Procedure
1. Connect input power (8V < VIN < 16V) and input ground to VIN and GND test pins respectively.
2. To use a jumper at “H” option to tie EN test pin for enabling the device. Inversely, to use a jumper at “L” option to tie EN test pin and ground GND for disabling the device.
3. Supply a 22kHz signal of the “TONE” pin to adjust the output tone signal.
4. Verify the output voltage between LNB and GND.
5. Connect an external load up to 0.45A to the VOUT and GND terminals and verify the output voltage and current.
Schematic, Bill of Materials & Board Layout
EVB Schematic Diagram
Bill of Materials
Reference
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Qty
|
Part Number
|
Description
|
Package
|
Manufacture
|
U1
|
1
|
RT5047AGSP
|
Voltage Regulator
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SOP-8
(Exposed Pad)
|
RICHTEK
|
C1, C2, C3, C4, C5, C6
|
6
|
|
10µF/50V
|
C-0805
|
|
C8
|
1
|
|
100nF/25V
|
C-0603
|
|
C9
|
1
|
|
0.1µF/50V
|
C-0805
|
|
C10
|
1
|
|
NC
|
|
|
R1, C7
|
2
|
|
NC
|
|
|
R2
|
1
|
|
NC
|
|
|
R3, R4, R6, R7
|
4
|
|
4.7k
|
R-0603
|
|
R5
|
1
|
|
12k
|
R-0603
|
|
R8
|
1
|
|
4k
|
R-0603
|
|
L1
|
1
|
|
10µH
|
L-NR8040_2
|
|
GP1, GP2, GP3
|
3
|
|
GND
|
SIP-1P-GP
|
|
GP4
|
1
|
|
VIN
|
SIP-1P-GP
|
|
GP5
|
1
|
|
LNB
|
SIP-1P-GP
|
|
D1, D2, D3
|
3
|
|
SS14
|
SS14
|
|
D4
|
1
|
|
SMDJ20A
|
D-SMC_DO-214_1
|
|
J1
|
1
|
|
TONE
|
SIP-3P
|
|
J2
|
1
|
|
NC
|
SIP-3P
|
|
J3
|
1
|
|
SEL
|
SIP-3P
|
|
J4
|
1
|
|
EN
|
SIP-3P
|
|
Z1, Z2
|
2
|
|
FK_1
|
FK_1
|
|
Z3, Z4, Z5, Z6
|
4
|
|
SIP-1P-M
|
SIP-1P-M
|
|
PCB Layout
Top View
Bottom View